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master's thesis
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FFT based audio processing in VHDL
Marijan Mautner (2018)
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics
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Mautner, M. (2018). VHDL implementacija FFTa za obradu audio signala (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:186133

Mautner, Marijan. "VHDL implementacija FFTa za obradu audio signala." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:186133

Mautner, Marijan. "VHDL implementacija FFTa za obradu audio signala." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:186133

Mautner, M. (2018). 'VHDL implementacija FFTa za obradu audio signala', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 23 August 2019, https://urn.nsk.hr/urn:nbn:hr:200:186133

Mautner M. VHDL implementacija FFTa za obradu audio signala [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2019 August 23] Available at: https://urn.nsk.hr/urn:nbn:hr:200:186133

M. Mautner, "VHDL implementacija FFTa za obradu audio signala", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:186133

Metadata
TitleVHDL implementacija FFTa za obradu audio signala
Title (english)FFT based audio processing in VHDL
AuthorMarijan Mautner
MentorTomislav Matić (mentor)
MentorLeon Šneler (mentor)
Committee memberTomislav Matić (predsjednik povjerenstva)
Committee memberIvan Aleksi (član povjerenstva)
Committee memberIvan Vidović (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2018-05-28, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Architecture of Computer Systems
Abstract
U radu je opisana implementacija FFT algoritma u FPGA tehnologiji. Opisana je primijenjena tehnologija i svi korišteni alati u razvoju. Demonstrirano je na koji se način izvršava FFT algoritam, matematička podloga rješenja i optimizacija algoritma za rad na sklopovlju. Opisane su sve korištene komponente i protokoli. Detaljno je opisan način rada svake konstruirane komponente. Dizajn sustava izveden je u Vivado razvojnom okruženju, a implementiran u ZYNQ 7000 SoC-u. Brzina i točnost sustava uspoređeni su s brzinom rada i točnošću MATLAB programskog paketa.
Abstract (english)
This Paper describes the implementation of FFT algorithm in FPGA technology. Paper gives a description of all technology and development tools used for development and implementation of design. Implementation and running of FFT algorithm are demonstrated as well as mathematical description of algorithm. All of created components are described in detail. Design of the implemented system has been made in VIVADO design suite and is implemented in ZYNQ 7000 SoC. Performance of the system is compared to that of a MATLAB.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:186133
Study programmeTitle: Računarstvo
Study programme type: sveučilišni
Study level: diplomski
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of usehttp://rightsstatements.org/vocab/InC/1.0/
Created on2018-06-11 10:24:10