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undergraduate thesis
VGA grafički upravljač s FPGA
2019. urn:nbn:hr:200:452841
Horvat, Matej
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Computer Engineering and Automation
Chair of Computer Engineering

Cite this document

Horvat, M. (2019). VGA grafički upravljač s FPGA (Undergraduate thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:452841

Horvat, Matej. "VGA grafički upravljač s FPGA." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2019. https://urn.nsk.hr/urn:nbn:hr:200:452841

Horvat, Matej. "VGA grafički upravljač s FPGA." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2019. https://urn.nsk.hr/urn:nbn:hr:200:452841

Horvat, M. (2019). 'VGA grafički upravljač s FPGA', Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 13 August 2022, https://urn.nsk.hr/urn:nbn:hr:200:452841

Horvat M. VGA grafički upravljač s FPGA [Undergraduate thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2019 [cited 2022 August 13] Available at: https://urn.nsk.hr/urn:nbn:hr:200:452841

M. Horvat, "VGA grafički upravljač s FPGA", Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:200:452841

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Metadata
TitleVGA grafički upravljač s FPGA
Title (english)VGA Graphic Controller on FPGA
AuthorMatej Horvat
MentorTomislav Matić (mentor)
Committee memberTomislav Matić (predsjednik povjerenstva)
Committee memberZdravko Krpić (član povjerenstva)
Committee memberIvan Aleksi (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Computer Engineering and Automation)
(Chair of Computer Engineering)
Osijek
Defense date and country2019-07-11, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Architecture of Computer Systems
Abstract
Implementacija VGA grafičkog upravljača korištenjem FPGA razvojnog sustava bila je cilj ovog završnog rada. Prilikom programiranja FPGA razvojnog sustava bilo je potrebno koristiti razvojno okruženje, a u ovom slučaju to razvojno okruženje bilo Xilinx-ov ISE Design Suite. FPGA koji je bio korišten je Nexys 3 Spartan-6 FPGA Trainer Board, koji posjeduje 8-bitni VGA priključak. Za ostvarenje tog cilja bilo je potrebno implementirati PS/2 protokol za komunikaciju tipkovnice s uređajem te radnu memoriju (RAM). Korisnik uz pomoć tipkovnice koja je spojena s FPGA unosi slova i/ili brojeve koji imaju vlastiti jedinstveni make-code, te se kôd, po kojem računalo prepoznaje o kojem je znaku riječ, sprema u radnu memoriju. Nakon toga se iz radne memorije uneseni podatci šalju VGA modulu, kako bi se željeni znakovi uspješno prikazali na ekranu jedan pored drugog. Korisnik uz pomoć backspace-a može brisati jedan po jedan znak s ekrana, a ukoliko je pritisnut enter svi znakovi s ekrana bit će obrisani. Znakovi se na crnu pozadinu ekrana ispisuju bijelom bojom, dimenzija piksela 6x8 (široki su 6 piksela a visoki 8). Nadogradnjom i/ili izmjenama ovog projekta moguće je kreirati jednostavne video igre, slične nekadašnjim igrama za konzole. Korištenjem kamere kao dodatni modul te nekog drugog FPGA koji podržava taj modul, moguće je napraviti procesiranje videa u stvarnome vremenu.
Abstract (english)
Implementation of VGA graphics controller using FPGA development board was the aim of this thesis. During the programming of FPGA development board it was necessary to use software tool and in this case it was Xilinx ISE Design Suite. The FPGA used here was Nexys 3 Spartan-6 FPGA Trainer Board which has 8-bit VGA port. To fulfill this task it was required to implement PS/2 communication protocol (device-to-host communication) and random-access memory module. By using the keyboard connected to FPGA the user inputs keys that have their unique make-code, by which the computer recognizes which key was pressed and stores this unique make-code in random access memory. Afterwards the information is forwarded from RAM to VGA module, so that each character is successfully shown on the screen in consecutive order. By using backspace the user can delete the characters from the screen one by one and if enter button is pressed all the characters from the screen will be deleted. The characters on the black screen are written in white color, their dimensions being 6x8 (6 wide and 8 tall). By upgrading and/or changing this project it is possible to create simple video games, similar to old console games. By using the camera as an additional module and other types of FPGA's which support that module, it is also possible to process videos in real time.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:452841
Study programmeTitle: Undergraduate University Study Programme in Computer Engineering
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2019-08-19 08:47:36