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master's thesis
Detekcija linija voznih traka na slici pomoću FPGA
2020. urn:nbn:hr:200:127650
Martin, Martin
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Computer Engineering and Automation
Chair of Automation and Robotics

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Martin, M. (2020). Detekcija linija voznih traka na slici pomoću FPGA (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:127650

Martin, Martin. "Detekcija linija voznih traka na slici pomoću FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2020. https://urn.nsk.hr/urn:nbn:hr:200:127650

Martin, Martin. "Detekcija linija voznih traka na slici pomoću FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2020. https://urn.nsk.hr/urn:nbn:hr:200:127650

Martin, M. (2020). 'Detekcija linija voznih traka na slici pomoću FPGA', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 01 February 2023, https://urn.nsk.hr/urn:nbn:hr:200:127650

Martin M. Detekcija linija voznih traka na slici pomoću FPGA [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2020 [cited 2023 February 01] Available at: https://urn.nsk.hr/urn:nbn:hr:200:127650

M. Martin, "Detekcija linija voznih traka na slici pomoću FPGA", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:200:127650

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Metadata
TitleDetekcija linija voznih traka na slici pomoću FPGA
Title (english)Lane detection in image based on FPGA
AuthorMartin Martin
MentorRatko Grbić (mentor)
MentorLeon Šneler (sumentor)
Committee memberRatko Grbić (predsjednik povjerenstva)
Committee memberMarijan Herceg (član povjerenstva)
Committee memberMario Vranješ (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Computer Engineering and Automation)
(Chair of Automation and Robotics)
Osijek
Defense date and country2020-10-09, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Architecture of Computer Systems
Abstract
U radu je opisana izrada i implementacija detekcije voznih traka uz korištenje FPGA tehnologije. Najprije dan pregled nekoliko postojećih rješenja detekcije vozne trake. Spomenuti radovi navode metode korištene za izradu sličnih sustava te FPGA kao prikladan sustav za rješavanje ovakve vrste problema. Nakon toga je u radu dan prijedlog algoritma za detekciju voznih traka te je isti implementiran u Matlab-u. Prema implementaciji iz Matlab-a dizajnirano je sklopovsko rješenje za detekciju vozne trake koristeći VHDL. Dizajn je sintetiziran i implementiran na Zynq-7000 SoC-u. Na procesorskom sustavu se izvršava upravljanje, unos slike i prikazivanje rješenja, dok se na programabilnom dijelu izvršava dizajnirani algoritam. Izvršena je verifikacija implementiranog dizajna te su na sustavu provedena mjerenja s obzirom na efikasnost detekcija linija na kolniku te s obzirom na brzinu izvođenja predloženog algoritma.
Abstract (english)
The paper describes the development and implementation of lane detection using FPGA technology. First, an overview of several existing lane detection solutions. The mentioned papers list the methods used for makeing similar or the same FPGA systems as a suitable system for solving these types of problems. After that, the paper presents a proposal for an algorithm for detecting lanes, which is implemented in Matlab. According to the implementation from Matlab, a hardware solution for detecting driving tracks using VHDL was designed. The design was synthesized and implemented on a Zynq-7000 SoC. On the processor system, control, image input and solution display are performed, while on the programmable part, the designed algorithm is executed. Verification of the implemented design was performed and measurements were performed on the system with regard to the efficiency of line detection on the pavement and with regard to the speed of execution of the proposed algorithm.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:127650
Study programmeTitle: Graduate University Study Programme in Computer Engineering
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2020-12-08 09:40:39