Josip Juraj Strossmayer University of Osijek Faculty of Electrical Engineering, Computer Science and Information Technology Osijek Department of Communications Chair of Multimedia Systems and Digital Television
Cite this document
Valek, I. (2018). Implementacija JPEG kodera zasnovanog na FPGA (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:334016
Valek, Igor. "Implementacija JPEG kodera zasnovanog na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:334016
Valek, Igor. "Implementacija JPEG kodera zasnovanog na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:334016
Valek, I. (2018). 'Implementacija JPEG kodera zasnovanog na FPGA', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:200:334016
Valek I. Implementacija JPEG kodera zasnovanog na FPGA [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:200:334016
I. Valek, "Implementacija JPEG kodera zasnovanog na FPGA", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:334016