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master's thesis
Asinkroni vremensko-digitalni pretvornik
2017. urn:nbn:hr:200:908710
Pešerović, Boris
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

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Pešerović, B. (2017). Asinkroni vremensko-digitalni pretvornik (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:908710

Pešerović, Boris. "Asinkroni vremensko-digitalni pretvornik." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2017. https://urn.nsk.hr/urn:nbn:hr:200:908710

Pešerović, Boris. "Asinkroni vremensko-digitalni pretvornik." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2017. https://urn.nsk.hr/urn:nbn:hr:200:908710

Pešerović, B. (2017). 'Asinkroni vremensko-digitalni pretvornik', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 14 January 2025, https://urn.nsk.hr/urn:nbn:hr:200:908710

Pešerović B. Asinkroni vremensko-digitalni pretvornik [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2017 [cited 2025 January 14] Available at: https://urn.nsk.hr/urn:nbn:hr:200:908710

B. Pešerović, "Asinkroni vremensko-digitalni pretvornik", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2017. Available at: https://urn.nsk.hr/urn:nbn:hr:200:908710

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Metadata
TitleAsinkroni vremensko-digitalni pretvornik
Title (english)Asynchronous time-to-digital converter
AuthorBoris Pešerović
MentorTomislav Matić (mentor)
Committee memberTomislav Matić (predsjednik povjerenstva)
Committee memberMarijan Herceg (član povjerenstva)
Committee memberMario Vranješ (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2017-09-25, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Abstract
U sklopu diplomskog rada projektiran je jedan vremensko-digitalni pretvornik te je implementiran na FPGA pločici i prikazani su rezultati mjerenja. Sklop je prošao kroz više promjena dok nisu dobiveni zadovoljavajući rezultati. TDC je projektiran u Quartus II kao shema i prebačena je u VHDL kod. TakoĎer je izvedena MATLAB simulacija jednostavnog vremensko digitalnog pretvornika i prikazani su rezultati simulacije
Abstract (english)
Time-to-digital converters are electronic devices which measure very short time intervals and can digitalise those intervals. They are often use din PLL circuits and particle physics and therefore are interesting. One kind of time-to-digital converter is implemented in FPGA circuit board and measurement results are shown in this thesis. The circuit went through some changes until satisfying results are obtained. TDC is designed in Quartus II as a schematic and then it is transfered to VHDL code. A simulation in MATLAB was made and the results are displayed in this paper.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:908710
Study programmeTitle: Graduate University Study Programme in Electrical Engineering; specializations in: Communications and Informatics, Power Engineering
Course: Communications and Informatics
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2017-10-23 15:57:13