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master's thesis
Detekcija lica na slici pomoću FPGA
2020. urn:nbn:hr:200:642919
Živković, Marko
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

Cite this document

Živković, M. (2020). Detekcija lica na slici pomoću FPGA (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:642919

Živković, Marko. "Detekcija lica na slici pomoću FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2020. https://urn.nsk.hr/urn:nbn:hr:200:642919

Živković, Marko. "Detekcija lica na slici pomoću FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2020. https://urn.nsk.hr/urn:nbn:hr:200:642919

Živković, M. (2020). 'Detekcija lica na slici pomoću FPGA', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 02 March 2021, https://urn.nsk.hr/urn:nbn:hr:200:642919

Živković M. Detekcija lica na slici pomoću FPGA [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2020 [cited 2021 March 02] Available at: https://urn.nsk.hr/urn:nbn:hr:200:642919

M. Živković, "Detekcija lica na slici pomoću FPGA", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:200:642919

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Metadata
TitleDetekcija lica na slici pomoću FPGA
Title (english)Face detection in the image using FPGA
AuthorMarko Živković
MentorMarijan Herceg (mentor)
MentorLeon Šneler (sumentor)
Committee memberMarijan Herceg (predsjednik povjerenstva)
Committee memberMario Vranješ (član povjerenstva)
Committee memberRatko Grbić (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2020-10-02, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Telecommunications and Informatics
Abstract
Algoritmi za detekciju lica na slici pronalaze primjenu u širokom spektru industrijske djelatnosti kao što su automobilska industrija, industrija računalnih igara, vojna industrija i druge. U sklopu ovog diplomskog rada bilo je potrebno razviti optimizirani algoritam za detekciju lica na slici različitih razlučivosti, opisati digitalni dizajn VHDL jezikom, te pomoću FPGA obaviti detekciju lica na slici. Nakon obrade već postojećih rješenja, predloženo je rješenje algoritma za detekciju lica na slici pomoću FPGA, počevši od samog razvoja i optimizacije algoritma u MATLAB-u do krajnjeg digitalnog dizajna opisanog VHDL kodom i implementiranog na ZYNQ SoC FPGA. Na kraju rada dani su rezultati testiranja iz kojih je vidljivo de je postignuta detekcija lica s točnošću od 79% na slici razlučivosti 320x240 pomoću FPGA signala takta od 55.56MHz za prosječno vrijeme detekcije od 1.15 s. Predloženo rješenje je moguće prilagoditi za druge razlučivosti i za detekciju drugih objekata.
Abstract (english)
Algorithms for face detection on the image find their application in a wide range of industrial activities such as the automotive industry, the computer game industry, the military industry and others. In this thesis, development an optimized algorithm for face detection on images of different resolutions, description of digital design in VHDL language, and face detection on images using FPGA are performed. After analysis of the existing solutions for the face detection algorithm, solution in this work was proposed. Elaboration of the proposed solutions starts from the development and optimization of the algorithm in MATLAB to the final digital design described in VHDL code and implemented on ZYNQ SoC FPGA. At the end of the paper, test results are given which show that face detection is achieved with an accuracy of 79% in the 320x240 resolution image using FPGA signal clock of 55.56MHz for an average detection time of 1.15 s. The proposed solution can be adjusted for other resolutions and for the detection of other objects.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:642919
Study programmeTitle: Graduate University Study Programme in Electrical Engineering; specializations in: Communications and Informatics, Power Engineering
Course: Communications and Informatics
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2020-12-08 09:33:10