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undergraduate thesis
Virtualno sklopovlje za FPGA razvojni sustav
2024. urn:nbn:hr:200:770555
Sedlar, Stjepan
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Software Engineering

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Sedlar, S. (2024). Virtualno sklopovlje za FPGA razvojni sustav (Undergraduate thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:770555

Sedlar, Stjepan. "Virtualno sklopovlje za FPGA razvojni sustav." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2024. https://urn.nsk.hr/urn:nbn:hr:200:770555

Sedlar, Stjepan. "Virtualno sklopovlje za FPGA razvojni sustav." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2024. https://urn.nsk.hr/urn:nbn:hr:200:770555

Sedlar, S. (2024). 'Virtualno sklopovlje za FPGA razvojni sustav', Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 21 January 2025, https://urn.nsk.hr/urn:nbn:hr:200:770555

Sedlar S. Virtualno sklopovlje za FPGA razvojni sustav [Undergraduate thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2024 [cited 2025 January 21] Available at: https://urn.nsk.hr/urn:nbn:hr:200:770555

S. Sedlar, "Virtualno sklopovlje za FPGA razvojni sustav", Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:200:770555

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Metadata
TitleVirtualno sklopovlje za FPGA razvojni sustav
Title (english)Virtual Hardware for FPGA Based Development Board
AuthorStjepan Sedlar
MentorTomislav Matić (mentor)
Committee memberTomislav Matić (predsjednik povjerenstva)
Committee memberGoran Knežević (član povjerenstva)
Committee memberŽeljko Hocenski (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Software Engineering)
Osijek
Defense date and country2024-09-11, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Architecture of Computer Systems
Abstract
Cilj ovog rada je bio uz pomoć Arduino platfome razviti virtualno sklopovlje koje bi se potencijalno moglo nadograditi i koristiti za udaljeno upravljanje FPGA razvojnim sustavom. Rad je realiziran uz pomoć Arduino Pro Micro pločice na način da se putem serijske komunikacije na Arduino pločicu šalje konfiguracijski niz znakova koji se potom pohranjuje u EEPROM mikroupravljača. U konfiguraciji se odabire koje izvedene nožice mikroupravljača će biti ulazne, a koje izlazne. Kada je ispravno konfigurirana, pločica se povezuje putem PMOD portova s FPGA sustavom gdje se prema konfiguraciji mikroupravljača postavljaju ulazi i izlazi FPGA razvojnog sustava.
Abstract (english)
The aim of this thesis was to develop virtual hardware using the Arduino platform that could potentially be upgraded and used for the remote controlling FPGA development board. This is accomplished using the Arduino Pro Micro board in a way that a configuration character string is sent to the Arduino board via serial communication, which is then stored in the EEPROM of the microcontroller. The configuration is used to determine which derived pins will be inputs and which outputs. When properly configured, the board is then connected to FPGA via PMOD ports, where the inputs and the outputs of the FPGA development board are set based on the microcontroller configuration.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:770555
Study programmeTitle: Undergraduate University Study Programme in Computer Engineering
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/sveučilišna provostupnik/prvostupnica (baccalaureus/baccalaurea) inženjerka računarstva (sveučilišni/sveučilišna provostupnik/prvostupnica (baccalaureus/baccalaurea) inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2024-10-07 11:33:57