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master's thesis
Programski model aritmetičko-logičke jedinice mikroprocesora
2015. urn:nbn:hr:200:581127
Toth, Goran
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Computer Engineering and Automation
Chair of Computer Engineering

Cite this document

Toth, G. (2015). Programski model aritmetičko-logičke jedinice mikroprocesora (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:581127

Toth, Goran. "Programski model aritmetičko-logičke jedinice mikroprocesora." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2015. https://urn.nsk.hr/urn:nbn:hr:200:581127

Toth, Goran. "Programski model aritmetičko-logičke jedinice mikroprocesora." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2015. https://urn.nsk.hr/urn:nbn:hr:200:581127

Toth, G. (2015). 'Programski model aritmetičko-logičke jedinice mikroprocesora', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 07 June 2021, https://urn.nsk.hr/urn:nbn:hr:200:581127

Toth G. Programski model aritmetičko-logičke jedinice mikroprocesora [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2015 [cited 2021 June 07] Available at: https://urn.nsk.hr/urn:nbn:hr:200:581127

G. Toth, "Programski model aritmetičko-logičke jedinice mikroprocesora", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2015. Available at: https://urn.nsk.hr/urn:nbn:hr:200:581127

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Metadata
TitleProgramski model aritmetičko-logičke jedinice mikroprocesora
Title (english)Programming model of arithmetic-logic unit in a microprocessor
AuthorGoran Toth
MentorŽeljko Hocenski (mentor)
MentorIvan Vidović (mentor)
Committee memberŽeljko Hocenski (predsjednik povjerenstva)
Committee memberIvan Aleksi (član povjerenstva)
Committee memberTomislav Keser (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Computer Engineering and Automation)
(Chair of Computer Engineering)
Osijek
Defense date and country2015-07-14, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Process Computing
Abstract
U ovom diplomskom radu upotrebom VHDL-a dizajniran je programski model 8-bitne aritmetičko-logičke jedinice mikroprocesora. Za dizajniranje i verifikaciju programskog modela, korišten je Xilinx ISE 14.7 programski paket te razvojni sustav Nexys 3. Realizirana je 21 različita operacija (aritmetičke operacije, logičke operacije, operacije pomaka i operacije usporedbe). Simulacija je provedena za niz testnih slučajeva koji su pokazali ispravan rad. Za potrebe testiranja modela implementiranog na razvojni sustav, dizajnirano je testno sučelje koje omogućava unos podataka putem tipkovnice i prikaz rezultata na 7-segmentnim pokaznicima. Implementirani model je testiran korištenjem istih testnih slučajeva kao za simulaciju i na taj način je dokazan ispravan rad.
Abstract (english)
This diploma thesis is describing a model design of a microprocessors 8-bit arithmeticlogic unit using VHDL. Xilinx ISE 14.7 software package is used for designing and verification of the program model. Nexys 3 development platform is used for implementation. 21 different operations are designed, like arithmetic operations, logic operations, shift operations and comparisons. The simulation was carried out for a number of test cases that showed proper operation. A interface that enables data entry via the keyboard was designed for testing purposes of the model implemented on the development system. The result is displayed on a 7-segment dispay unit. The implemented model was tested using the same test cases as the simulation and the results are showing correct model operation.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:581127
Study programmeTitle: Graduate University Study Programme in Computer Engineering
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2016-08-03 10:12:55